EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

 

This section provides designers with the data sheet specifications for Arria? GX devices. They contain feature definitions of the transceivers, internal architecture,configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Arria II GX devices. EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

 

The Arria? GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria II GX devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode.  EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358The transceivers build upon the success of the Stratix? II GX family. EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358.The Arria II GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols. EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

 

The key features of Arria II GX devices include:

EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

■ Transceiver block features

■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps.

■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels

■ Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode

■ Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation

■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers

■ Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode)

■ Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices

■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO

■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding

■ Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array

■ Channel aligner compliant with XAUI .EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

 

The basic building block of logic in the Arria II GX architecture is the ALM. The ALM provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can implement various combinations of two functions. This adaptability allows the ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions.EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

Dedicated circuitry is built into Arria II GX devices to automatically perform error detection. This circuitry constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a reconfiguration cycle. You can select the desired time between checks by adjusting a built-in clock divider. EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

 

In addition to the six I/O registers in each IOE, Arria II GX devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces, including DDR,DDR2 SDRAM, and SDR SDRAM. In every Arria II GX device, the I/O banks at the top(Banks 3 and 4) and bottom (Banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–23 shows the number of DQ and DQS buses that are supported per device.EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358

 

The Arria II GX device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom. EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358 Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed phase circuitry on the top of the device and clock pins CLK[7..4]p feed phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits. Figure 2–77 shows the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. EP2AGX65CU17I5N Altera IC ARRIA II GX FPGA 65K FBGA358