EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208

 

EPF10K30E   EPF10K50E   EPF10K50S   EPF10K100B   EPF10K100E

EPF10K130E  EPF10K200E  EPF10K200S

 

EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208

Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208.The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and designverification. FLEX 10KE reconfigurability eliminates inventory manag.ement for gate array designs and generation of test vectors for fault coverage.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208

Table 5 shows FLEX 10KE performance for some common designs. All performance values were obtained with Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file.Similar to the FLEX 10KE architecture, embedded gate arrays are the fastest-growing segment of the gate array market. As with standard gate EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208 arrays, embedded gate arrays implement general logic in a conventional “sea-of-gates” architecture. Additionally, embedded gate arrays have dedicated die areas for implementing large, specialized functions. By embedding functions in silicon, embedded gate arrays reduce die area and increase speed when compared to standard gate arrays. While embedded megafunctions typically cannot be customized, FLEX 10KE devices are programmable, providing the designer with full control over embedded megafunctions and general logic, while facilitating iterative design changes during debugging.

EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208 Each FLEX 10KE device contains an embedded array and a logic array. The embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (DSP), wide data-path manipulation, microcontroller applications, and datatransformation functions. The logic array performs the same function as the sea-of-gates in the gate array and is used to implement general logic such as counters, adders, state machines, and multiplexers. The combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208

FLEX 10KE devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers the EPC1, EPC2, and EPC16 configuration devices, which configure FLEX 10KE devices via a serial data stream.Configuration data can also be downloaded from system RAM or via the Altera BitBlasterTM, ByteBlasterMVTM, or MasterBlaster download cables.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208.After a FLEX 10KE device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 85 ms, real-time changes can be made during system operation.

EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208.FLEX 10KE devices contain an interface that permits microprocessors to configure FLEX 10KE devices serially or in-parallel, and synchronously or

asynchronously. The interface also enables microprocessors to treat a FLEX 10KE device as memory and configure it by writing to a virtual memory location, making it easy to reconfigure the device.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208

 

Each FLEX 10KE device contains an enhanced embedded array to implement memory and specialized logic functions, and a logic array to implement general logic.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208.The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 4,096 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions, such as multipliers, microcontrollers,state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208.The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect. An LE consists of a four-input look-up table (LUT), a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic—such as 8-bit counters, address decoders, or state machines—or combined across LABs to create larger logic blocks. Each LAB represents about 96 usable gates of logic. EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208.Signal interconnections within FLEX 10KE devices (as well as to and from device pins) are provided by the FastTrack Interconnect routing structure, which is a series of fast, continuous row and column channels that run the entire length and width of the device.EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208 Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect routing structure. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals.When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 0.9 ns and hold times of 0 ns. As outputs, these registers provide clock-to-output times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208.

 

To support high-speed designs, FLEX 10KE devices offer optional ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)used to increase design speed and reduce resource usage. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by resource sharing within the device. The ClockBoost feature

EPF10K100BQC208-3DX Altera IC FLEX 10KE FPGA 100K PQFP208 allows the designer to distribute a low-speed clock and multiply that clock on-device. Combined, the ClockLock and ClockBoost features provide significant improvements in system performance and bandwidth.