EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

 

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EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

APEX II devices integrate high-speed differential I/O support using the True-LVDS interface.

EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33 .The dedicated serializer, deserializer, and CDS circuitry in the True-LVDS interface support the LVDS, LVPECL,HyperTransport, and PCML I/O standards. Flexible-LVDS pins located in regular user I/O banks offer additional differential support, increasing the total device bandwidth. This circuitry, together with enhanced IOEs and support for numerous I/O standards, allows APEX II devices to meet high-speed interface requirements.EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

 

APEX II devices also include other high-performance features such as bidirectional dual-port RAM, CAM, general-purpose PLLs, and numerous global clocks. EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

 

The logic, circuitry, and interconnects in the APEX II architecture are configured with CMOS SRAM elements. APEX II devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for fault coverage. Instead, the designer can focus on simulation and design verification. In addition, the designer does not need to manage inventories of different ASIC designs;APEX II devices can be configured on the board for the specific functionality required. EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

 

APEX II devices are configured at system power-up with data either stored in an Altera configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices, which configure APEX II devices via a serial data stream. EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33. The enhanced configuration devices can configure any APEX II device in under 100 ms. EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33.Moreover, APEX II devices contain an optimized interface that permits microprocessors to configure APEX II devices serially or in parallel, synchronously or asynchronously. This interface also enables microprocessors to treat APEX II devices as memory and to configure the device by writing to a virtual memory location, simplifying

 

EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

APEX II devices also support a new byte-wide, synchronous configuration scheme at speeds of up to 66 MHz using EPC16 configuration devices or a microprocessor. This parallel configuration reduces configuration time by using eight data lines to send configuration data versus one data line in serial configuration.EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33.APEX II devices support multi-voltage configuration; device configuration can be performed at 3.3 V and 2.5 V or 1.8 V.

EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33.After an APEX II device has been configured, it can be reconfigured incircuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications.

EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

 

APEX II devices are supported by the Altera Quartus II development system: a single, integrated package that offers hardware description language (HDL) and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800

 

EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

The Quartus II software includes the LogicLock incremental design feature. The LogicLock feature allows the designer to make pin and timing assignments, verify functionality and performance, and then set constraints to lock down the placement and performance of a specific

block of logic using LogicLock constraints. Constraints set by the LogicLock function guarantee repeatable placement when implementing a block of logic in a current project or exporting the block to another project. The constraints set by the LogicLock feature can lock down logic to a fixed location in the device. The LogicLock feature can also lock the logic down to a floating location, and the Quartus II software determines the best relative placement of the block to meet design requirements.Adding additional logic to a project will not affect the performance of blocks locked down with LogicLock constraints.EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33.The Quartus II software provides NativeLink interfaces to other industrystandard PC- and UNIX workstation-based EDA tools. For example,designers can open the Quartus II software from within third-party design tools. The Quartus II software also contains built-in optimized synthesis libraries; synthesis tools can use these libraries to optimize designs for APEX II devices. For example, the Synopsys Design Compiler library, supplied with the Quartus II development system, includes DesignWare functions optimized for the APEX II architecture. EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33

 

APEX II devices incorporate LUT-based logic, product-term-based logic,memory, and high-speed I/O standards into one device. Signal interconnections within APEX II devices (as well as to and from device pins) are provided by the FastTrack interconnect—a series of fast,continuous row and column channels that run the entire length and width of the device..EP2A25F33C-9N Altera IC APEX II FPGA 25K FBGA33.Each I/O pin is fed by an IOE located at the end of each row and column of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer and six registers that can be used for registering input, output, and output-enable signals. When used with a dedicated clock pin, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM and ZBT and QDR SRAM

devices.