EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

 

 

EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

Programmable logic device (PLD) manufactured using a 0.15-m alllayer copper-metal fabrication process

– 25 to 35% faster design performance than APEX TM 20KE devices

– Pin-compatible with APEX 20KE devices

– High-performance, low-power copper interconnect

– MultiCore

architecture integrating look-up table (LUT) logic and embedded memory Preliminary

 

– LUT logic used for register-intensive functions

– Embedded system blocks (ESBs) used to implement memory

functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)

 

High-density architecture

– 100,000 to 1.5 million typical gates (see Table 1)

– Up to 51,840 logic elements (LEs)

– Up to 442,368 RAM bits that can be used without reducing available logic

EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

 

Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer the MultiCore architecture, which combines the strengths of LUT-based and product-term-based devices with an enhanced memory structure.LUT-based logic provides optimized performance and efficiency for datapath,register-intensive, mathematical, or digital signal processing (DSP) designs.

 

EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and productterm-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20KC architecture uniquely suited for SOPC designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20KC device.EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

 

APEX 20KC devices include additional features such as enhanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry. Table 7 shows the features included in APEX 20KC devices.EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N.All APEX 20KC devices are reconfigurable and are 100% tested prior to shipment. As a result, test vectors do not have to be generated for faultcoverage purposes. Instead, the designer can focus on simulation and

design verification. In addition, the designer does not need to manage inventories of different application-specific integrated circuit (ASIC)designs; APEX 20KC devices can be configured on the board for the specific functionality required. EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

 

APEX 20KC devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

Altera offers in-system programmability (ISP)-capable EPC16,EPC2, and EPC1 configuration devices, which configure APEX 20KC devices via a serial data stream. EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N.

Moreover, APEX 20KC devices contain an optimized interface that permits microprocessors to configure APEX 20KC devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat APEX 20KC devices as memory and configure the device by writing to a virtual memory location, making reconfiguration easy. EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

 

After an APEX 20KC device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N.APEX 20KC devices are supported by the Altera Quartus II development system, a single, integrated package that offers HDL and schematic design

entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations..EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

 

The Quartus II software provides NativeLink interfaces to other industrystandard PC- and UNIX workstation-based EDA tools. For example,designers can invoke the Quartus II software from within third-party design tools. Further, the Quartus II software contains built-in optimized synthesis libraries; synthesis tools can use these libraries to optimize designs for APEX 20KC devices. For example, the Synopsys Design Compiler library, supplied with the Quartus II development system,includes DesignWare functions optimized for the APEX 20KC

architecture.EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N

 

APEX 20KC devices incorporate LUT-based logic, product-term-based logic, and memory into one device on an all-copper technology process.Signal interconnections within APEX 20KC devices (as well as to and from device pins) are provided by the FastTrack interconnect—a series of fast, continuous row and column channels that run the entire length and width of the device.

EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N.Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer and a register that can be used as either an input or output register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional

performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,66-MHz PCI compliance; JTAG BST support; slew-rate control; and tri-state buffers. APEX 20KC devices offer enhanced I/O support,including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V AGP I/O standards.

 

APEX 20KC devices provide four dedicated clock pins and four dedicated input pins that drive register control inputs. These signals ensure efficient distribution of high-speed, low-skew control signals, which use dedicated routing channels to provide short delays and low skews. Four of the dedicated inputs drive four global signals. These four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or internally generated asynchronous clear signals with high fan-out. EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N .The dedicated clock pins featured on the APEX 20KC devices can also feed logic.  EP20K200CP208I8N Altera IC APEX 20KC FPGA 200K P208I8N.The devices also feature ClockLock and ClockBoost clock management circuitry.