IBM Demos In-Memory Massively Parallel Computing

IBM Demos In-Memory Massively Parallel Computing

LAKE WALES, Fla. — Today’s experimental non-von Neumann computing architectures mostly make use of memristive devices modeled on the human brain; they do not separate data memory from computing hardware and thus avoid the inefficiency of von Neumann computers’ repeated load/store operations. Now IBM Research (Zurich) has demonstrated a way to mass-produce 3-D stacks of phase-change memory (PCM) to perform memristive calculations 200 times faster than von Neumann computers. The in-memory coprocessor uses algorithms that exploit the dynamic physics of phase-change memories simultaneously on myriad cells, similar to the way millions of neurons and trillions of synapses in the brain operate in parallel.

The development, which IBM will demonstrate in December at the International Electronic Devices Meeting (IEDM), could return the company to the brink of hardware dominance.

Phase-change memory chip (center) with integrated read/write memory control circuitry for performing specialized simultaneous crystallization-dynamics operations on memory cells using sublithographic bottom electrodes. Source: IBMPhase-change memory chip (center) with integrated read/write memory control circuitry for performing specialized simultaneous crystallization-dynamics operations on memory cells using sublithographic bottom electrodes.
Source: IBM

“What we have demonstrated is that computational primitives can do deep learning using non-von Neumann processors,” IBM Fellow Evangelos Eleftheriou told EE Times. “So far, we’ve shown a speedup of 200 times for our k-means clustering algorithm, but we have many other computational primitives on the way that we will demonstrate later this year.”

The new paradigm combines PCM crystallization dynamics with an acceleration methodology called in-memory computing, which loads all data into RAM instead of swapping data sets into and out of mass memory (hard drives or flash). IBM’s approach does not force the in-memory values through the von Neumann bottleneck of a central processing unit; rather, it leaves the initial-state memory values in each PCM cell and uses a specialized memory controller to perform simultaneous, parallel operations on the cells. Calculations are performed in place by harnessing the physical properties of the phase-change RAMs. 

Diagram of IBM's support circuitry (green and blue) for its PCM devices (brown), which perform simultaneous operations on cells (details, right). Source: IBMDiagram of IBM�s support circuitry (green and blue) for its PCM devices (brown), which perform simultaneous operations on cells (details, right).
Source: IBM

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