MAX 3000A
EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
Feature:
EPM3032A EPM3064A EPM3128A
EPM3256A EPM3512A
EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX? architecture
MAX 3000A
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
■ High–density PLDs ranging from 600 to 10,000 usable gates
■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages
■ Hot–socketing support
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ Industrial temperature range
EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based
MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz.
MAX 3000A devices
in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification
EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
The
MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register withindependently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and high–speed parallel expander product terms to provide up to 32 product terms per macrocell. EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
MAX 3000A devices can be programmed on Windows–based PCs with an Altera Logic Programmer card, MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208 Programmable Speed/Power Control MAX 3000A devices offer a power–saving mode that supports low-power operation across user–defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more because most logic applications require only a small fraction of all gates to operate at maximum frequency. EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
The designer can program each individual macrocell in a
MAX 3000A device for either high–speed or low–power operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tACL, tEN, tCPPW and tSEXP parameters. EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
Open–Drain Output Option
MAX 3000A devices provide an optional open–drain (equivalent to open-collector) output for each I/O pin. This open–drain output enables the device to provide system–level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired–OR plane. EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208 Open-drain output pins on MAX 3000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high VIH. When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby meeting CMOS requirements. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor EPM3256AQI208-7N Altera IC MAX 3000A CPLD 256 PQFP208
MAX 3000A