Stratix Device

EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956

 

Stratix Device Features —

EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956

 

This section provides the data sheet specifications forStratix? devices.They contain feature definitions of the internal architecture,configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices. EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956

 

TheStratix? family of FPGAs is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs). EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956 .Stratix devices are available in space-saving FineLine BGA? and ball-grid array (BGA) packages (see Tables 1–3 through 1–5). All Stratix devices support vertical migration within the same package (for example, you can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672- pin BGA package). Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, you must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migrational. The Quartus? II software can automatically cross reference and place all pins except differential pins for migration when given a device migration list. You must use the pinouts for each device to verify the differential placement migration. A future version of the Quartus II software will support differential pin migration. EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956

 

Stratix devices are available in space-saving FineLine BGA? and ball-grid array (BGA) packages (see Tables 1–3 through 1–5). All Stratix devices support vertical migration within the same package (for example, you can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672- pin BGA package). Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, you must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migrational. The Quartus? II software can automatically cross reference and place all pins except differential pins for migration when given a device migration list. You must use the pinouts for each device to verify the differential placement migration. A future version of the Quartus II software will support differential pin migration. EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956 Power Consumption Altera? offers two ways to calculate power for a design: the Altera web power calculator and the PowerGaugeTM feature in the Quartus? II software. EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956 .The interactive power calculator on the Altera web site is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II software PowerGauge feature allows you to apply test vectors against your design for more accurate power consumption modeling. EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956

In both cases, these calculations should only be used as an estimation of power, not as a specification. Stratix devices require a certain amount of power-up current to successfully power up because of the small process geometry on which they are fabricated. EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956.Table 4–34 shows the maximum power-up current (ICCINT) required to power a Stratix device. This specification is for commercial operating conditions. Measurements were performed with an isolated Stratix device on the board to characterize the power-up current of an isolated EP1S60F956C7 Altera IC STRATIX FPGA 60K LE FBGA956

DSP Block Interface

 

Stratix device DSP block outputs can cascade down within the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. You can cascade DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than four taps, with additional adder stages implemented in LEs.If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator stages are implemented in LEs. Each DSP block can route the shift register chain out of the block to cascade two full columns of DSP blocks.