EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

 

 

The Stratix II GX family of devices is Altera’s third generation of FPGAs to combine high-speed serial transceivers with a scalable,high-performance logic array. EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152.Stratix II GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock and data recovery unit (CRU) technology and embedded SERDES capability at data rates of up to 6.375 gigabits per second (Gbps). The transceivers are grouped into four-channel transceiver blocks and are designed for low power consumption and small die size. EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

 

technology is built upon the Stratix II architecture and offers a 1.2-V logic array with unmatched performance, flexibility, and time-to-market capabilities. This scalable, high-performance architecture makes Stratix II GX devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications.EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

 

■ Main device features:EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

● TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 550 MHz

● Up to 16 global clock networks with up to 32 regional clock networks per device region

● High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions,and finite impulse response (FIR) filters

● Up to four enhanced PLLs per device provide spread spectrum,programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplication and phase shifting

● Support for numerous single-ended and differential I/O standards

● High-speed source-synchronous differential I/O support on up to 71 channels

● Support for source-synchronous bus standards, including SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI,and CSIX-L1

● Support for high-speed external memory, including quad data rate (QDR and QDRII) SRAM, double data rate (DDR and DDR2) SDRAM, and single data rate (SDR) SDRAM

EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

 

EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

All Stratix II GX devices support vertical migration within the same package. Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, you must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migratable. Table 1–3 lists the Stratix II GX device package sizes.EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

 

Stratix? II GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 6.375-Gbps serial transceiver channels. Each Stratix II GX transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. The transceivers deliver bidirectional point-to-point data transmissions, with up to 51 Gbps (6.375 Gbps per channel) of full-duplex data transmission per transceiver block. Figure 2–1 shows the function blocks that make up a transceiver channel

within the Stratix II GX device.EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

 

The Stratix II GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standard at rates up to 6.375 Gbps. The common mode voltage of the receiver input buffer is programmable between 0.85 V and 1.2 V.You must select the 0.85 V common mode voltage for AC- and DC-coupled PCML links and the 1.2 V common mode voltage for DC-coupled LVDS links.

Other Transceiver Features Other important features of the Stratix II GX transceivers are the power down and reset capabilities, external voltage reference and bias circuitry,

and hot swapping.EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152

 

The Stratix II GX device uses the calibration block to calibrate the on-chip termination for the PLLs and their associated output buffers and the terminating resistors on the transceivers. The calibration block counters the effects of process, voltage, and temperature (PVT). The calibration

block references a derived voltage across an external reference resistor to calibrate the on-chip termination resistors on the Stratix II GX device. The calibration block can be powered down. However, powering down the calibration block during operations may yield transmit and receive data errors.EP2SGX60EF1152C3N Altera IC STRATIX II GX 60K FBGA1152