Cyclone FPGA
EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100
EP1C3 EP1C4 EP1C6
EP1C12 EP1C20
Introduction
The Cyclone field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards,including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100
Features The Cyclone device family offers the following features:
■ 2,910 to 20,060 LEs, see Table 1–1
■ Up to 294,912 RAM bits (36,864 bytes)
■ Supports configuration through low-cost serial configuration device
■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard
■ High-speed (640 Mbps) LVDS I/O support
■ Low-speed (311 Mbps) LVDS I/O support
■ 311-Mbps RSDS I/O support
■ Up to two PLLs per device provide clock multiplication and phase shifting
■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row
■ Support for external memory, including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM
■ Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100
Functional Description
Cyclone? devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks. EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100 The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device.Cyclone devices range between 2,910 to 20,060 LEs.M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM. EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains(used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100
Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support. EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100
Logic Elements
The smallest unit of logic in the Cyclone architecture, the LE, is compact and provides advanced features with efficient logic utilization. EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100 .Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by a LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100
MultiTrack Interconnect
In the Cyclone architecture, connections between LEs, M4K memory blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100 The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different speeds used for inter- and intra-design block connectivity.EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100 .The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance.DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100 .The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimiza
EP1C3T100I6N Altera IC CYCLONE FPGA 2910 LE TQFP100