Introduction

Altera
EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

devices provide performance that is consistent from simulation to application. Before programming a device, you can determine the worstcase timing delays for any design. You can calculate propagation delays either with the MAX+PLUS,EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

 

EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP
models given in this application note and the timing parameters listed in individual device data sheets. Both methods yield the same results.  This application note defines internal and external timing parameters, and illustrates the timing models for the MAX 5000 ,EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP (including MAX 5000A), and Classic device families. Familiarity with device architecture and characteristics is assumed. Refer to the device family data sheets in this data book for complete descriptions of the architectures, and for the specific values of the timing parameters listed in this application note.EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

Within a device, the timing delays contributed by individual architectural elements are called internal timing parameters, which cannot be measured explicitly. All internal timing parameters are shown in italic type. The following section defines the internal timing parameters for MAX 5000 and Classic devices, and applies to both device families unless otherwise indicated. Classic devices include the EP610, EP610I, EP910, EP910I , and EP1810 devices only.EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

 

EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP
devices provide performance that is consistent from simulation to application. Before programming a device, you can determine the worstcase timing delays for any design. You can calculate propagation delays either with the MAX+PLUS II Timing Analyzer or with the timing models given in this application note and the timing parameters listed in individual device data sheets.EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP Both methods yield the same results. This application note defines internal and external timing parameters, and illustrates the timing models for the MAX 5000 (including MAX 5000A), and Classic ™EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

device families.
EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

Familiarity with device architecture and characteristics is assumed. Refer to the device family data sheets in this data book for complete descriptions of the architectures, and for the specific values of the timing parameters listed in this application note.  Internal Timing Parameters Within a device, the timing delays contributed by individual architectural elements are called internal timing parameters, EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIPwhich cannot be measured explicitly. All internal timing parameters are shown in italic type. The following section defines the internal timing parameters for MAX 5000 and Classic devices, and applies to both device families unless otherwise indicated. Classic devices include the EP610, EP610I, EP910,  EP910I , and EP1810 devices only.EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

 

EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP
Timing models are simplified block diagrams that illustrate the propagation delays through Altera devices. Logic can be implemented on different paths. You can trace the actual paths used in your design by examining the equations listed in the MAX+PLUS II Report File the project. You can then add up the appropriate internal timing parameters to calculate the propagation delays through the device.EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP

The MAX 5000 architecture supports many functions. The macrocell array provides registered, combinatorial, or flow-through latch operation. The registers can be clocked from a global clock or through product-term array clocks, and can be asynchronously preset and cleared. Separate product terms control the output enable and logic inversion signals. The array of shared expander product terms provides additional product terms to implement complex logic.  The MAX 5000 family has single- and multi-LAB devices. Figure 1 shows the timing model for the single-LAB EPM5032 device  Conclusion The MAX 5000 and Classic device architectures have fixed internal timing delays that are independent of routing. Therefore, you can determine the worst-case timing delays for any design before programming a device.  Total delay paths can be expressed as the sums of internal timing delays. Timing models illustrate the internal delay paths for devices and show how these internal timing parameters affect each other. You can use the MAX+PLUS II Timing Analyzer to automatically calculate delay paths, or hand-calculate delay paths by adding the internal timing parameters for an appropriate timing model. With the ability to predict worst-case timing delays, you can be confident of a design’s in-system timing performance.EPM5032DC-17N Altera IC MAX 5000 CPLD CerDIP