SAN FRANCISCO—The requirement for lithography double patterning on many layers makes moving to the 20-nm node a major undertaking that will require customers to invest in new design tool sets, according to Saleem Haider, senior director of marketing for physical design and DFM at Synopsys Inc.
In an interview at the Design Automation Conference (DAC) Monday (June 4), Haider said that in his 15 years at Synopsys the company has always taken the position that migration to a new node was an incremental, rather than revolutionary, change. Competitors, meanwhile, eager to gain market share in physical design implementation, have tried to convince customers that each node migration ushered in a brand new world, Haider said.
"For the first time, we agree with them," Haider said. "Twenty nanometer is going to be very different. It's not an incremental change."
Gary Smith, chief analyst at Gary Smith EDA, said the requirement to invest in new tool sets could be an opportunity for competitors to wrest market share away from EDA's biggest firm. "It's a complete change," he said.
Because of the resolution limitations of 193-nm immersion lithography, several critical layers of 20-nm designs will need to employ double patterning—two passes through the lithography scanner with two separate photomasks. This technique is costly—requiring double the mask investment for these layers—and more time consuming. It also requires creating a design layout that can be split into two parts, one for each pass through the scanner, according to Haider.
"The requirement for double patterning places a very large burden on the tool chain," Haider said. The requirement necessitates enhancements in placement and routing of transistors, layout generation and verification, among others, Haider said.
Haider concedes that joining competitors in saying that 20-nm requires re-tooling provides an opportunity for competitors envious of Synopsys' position in physical design. But he maintains that Synopsys can actually increase its market share through the transition because of the foundation of its IC Compiler place and route tool. He noted that in addition to supporting double patterning compliant layout generation, tools will still need to support the same or even more stringent requirements as they did at 28-nm for things like power, performance and die size.
"We are pretty excited about 20-nm," Haider said. "I think it's really going to open the gap between us and the field even more."
But Smith said Synopsys is at risk of losing market share as customers re-tool for 20-nm. As an example, he cited physical design tool vendor AtopTech Inc., which has captured attention and market share with its Aprisa place-and-route tool in recent years.
Smith said concern over shoring up its design flow was what motivated Synopsys to make the
recent $523 million acquisition of longtime rival Magma Design Automation Inc. "They were getting some holes in their flow," Smith said. "The big one was timing analysis."
Smith said the acquisition of Magma made sense strategically because it strengthened Synopsys in product areas where it was weak.
Haider said Synopsys has worked with some of its more leading edge customers on 20-nm test chips, several of which have already been completed. By the end of this year, he estimated that about two dozen 20-nm designs will have been completed.
Synopsys has also begun early development work on 14-nm technology, Haider said. At that node, it is likely that some layers will require triple patterning, he said. Some have suggested that by the 10-nm, quadruple of even quintuple patterning of some layers will be required if extreme ultraviolet (EUV) lithography isn't ready to go into production. Lithography tool vendor ASML has put out several pre-production EUV tools but still working with source providers to develop a power source powerful and stable enough to support volume throughput.