MANHASSET, NY -- Cadence Design Systems claims that Netronome designers achieved a 29 percent reduction in power consumption using Cadence's latest Encounter 11.1 technology thereby providing performance advantage on its low-power "green" SoCs targeting the secure virtual cloud and data center markets.
According to Netronome, its OEM customers have tremendous constraints on power budgets, which required the company to optimize its high-performance 40Gbps NFPs for low-power consumption for use in their customers' switches, routers, load balancing and cyber-security platforms.
"Using the complete Cadence Encounter RTL-to-GDSII flow, we were able to tape out a complex 1.4 GHz 40-core micro-engine-based Network Flow Processor on schedule, achieving a 29 percent power savings and 10 percent improvement in timing," said Jim Finnegan, senior vice president, Silicon Engineering at Netronome.
Netronome engineers were particularly impressed with the newly integrated Clock Concurrent Optimization (CCOpt) technology in the Encounter flow and its unique ability to optimize clocks and data-path simultaneously, thus eliminating several manual design steps and achieving superior performance, power and area results on their design.
Netronome engineers were tasked with improving chip power efficiencies across multi-mode, multi-corner and on-chip variation scenarios. Implementing robust clock trees that consume less dynamic switching and static leakage power without compromising on performance was difficult under such extreme requirements.
Furthermore, as chip power consumption increases, it costs more to design, fabricate, operate and cool devices and systems. Clocks are the backbone of all digital chips, and a fundamentally different approach to clock construction and optimization was needed.
According to Cadence, traditional clock tree synthesis (CTS) tools and methodologies are insufficient for advanced node, high-performance designs due to the growing gap between pre- and post-CTS design timing. CCOpt technology bridges the gap by re-focusing CTS directly on timing -- not skew minimization -- and combining this timing-driven CTS with concurrent logic/physical optimization.
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