LONDON – EDA software provider Synopsys Inc. (Mountain View, Calif.) has announced its DesignWare family of circuit designs is being ported to a low-leakage 40-nm process technology in use at Semiconductor Manufacturing International Corp. (Shanghai, China). The low-leakage 40LL process is aimed at SoCs for mobile markets.
The circuits include embedded memory, logic, analog and interface IP for protocols such as USB 2.0/3.0, PCI Express 2.0/1.1, MIPI, SATA, DDR, and HDMI.
The SMIC 40LL process technology combines advanced immersion lithography, strain engineering, ultra shallow junction and ultra low-k dielectric.
"Our first-pass silicon success with Synopsys' DesignWare USB, HDMI and audio codec IP, where all critical performance metrics meet or exceed the target specifications, demonstrates the stability and maturity of SMIC's 40LL technology," said Chris Chi, chief business officer at SMIC, in a statement.
Much of the DesignWare IP is available now with all due to be available in the fourth quarter of 2012.
Related links and articles:
www.synopsys.com
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